FIG. 1 illustrates a circuit diagram for a prior art six transistor (6T) memory cell 1 for a static random access memory (SRAM). As illustrated in FIG. 1, memory cell 1 has two cross-coupled inverters 10 and 20 coupled between a supply voltage Vcc node and a ground node to generate complementary signals at storage nodes 11 and 21. Inverter 10 has a pull-up p-channel field effect transistor (PFET) 12 and a pull-down n-channel FET (NFET) 14. The gates of PFET 12 and NFET 14 are both coupled to receive a signal at storage node 21 to generate an inverted signal at storage node 11. Similarly, inverter 20 has a pull-up PFET 22 and a pull-down NFET 24. The gates of PFET 22 and NFET 24 are both coupled to receive a signal at storage node 11 to generate an inverted signal at storage node 21. The complementary signals at storage nodes 11 and 21 represent a single binary value depending on which signal is at which storage node 11 or 21.
Memory cell 1 also has NFETs 16 and 26 to access memory cell 1 to read a binary value from and/or write a binary value to memory cell 1. The gate of NFET 16 is coupled to receive a signal on a word line 30 to couple storage node 11 to a bit line 31. The gate of NFET 26 is coupled to receive a signal on word line 30 to couple storage node 21 to a bit line 32. Memory cell 1 may then be accessed by sensing the complementary signals on bit lines 31 and 32 to read the binary value stored by memory cell 1 or by asserting complementary signals on bit lines 31 and 32 to write a binary value to memory cell 1. NFETs 16 and 26 are known as transfer, access, or pass transistors.
To speed reading the binary value, PFETs 41, 42, and 43 are activated in response to a signal on a precharge line 40 to precharge bit lines 31 and 32 by coupling them to a supply voltage Vcc node. The binary value may then be read as soon as bit line 31 is pulled down by NFET pair 14 and 16 or bit line 32 is pulled down by NFET pair 24 and 26 without having to wait for the other bit line 32 or 31 to be pulled up.
Memory cell 1 is to be designed to meet a minimum level of stability for a given memory size and process. Read stability can be loosely defined as the probability that memory cell 1 will flip its stored binary value during a read operation. Memory cell 1 is more susceptible to noise during a read operation because the voltage at the low storage node, such as storage node 21 for example, will rise due to the voltage division by NFETs 24 and 26 between precharged bit line 32 and the ground node when NFET 26 is activated by a high signal on word line 30. Mismatch in threshold voltage Vth of neighboring transistors, such as NFETs 24 and 26 for example, reduces the available static noise margin (SNM) of memory cell 1 and therefore reduces read stability of memory cell 1. As transistor dimensions are scaled, variability in the number and location of channel dopant atoms can result in restrictive electrical deviations in transistor threshold voltages Vth.
One technique to reduce noise at storage node 21, for example, and therefore help increase read stability of memory cell 1, is to increase the ratio of the transconductance of NFET 24 relative to that of NFET 26. This ratio is known as the cell ratio. A cell ratio of 1.5 to 2.0 is typical. The cell ratio in this example may be increased, for example, by sizing NFET 24 to have a larger width than NFET 26. The cell ratio in this example may also be increased, for example, by boosting the supply voltage for the cross-coupled inverters relative to the voltage supplied to precharge bit lines 31 and 32.
Because a write is performed by discharging the voltage at the high storage node, such as storage node 21 for example, through NFET 26, write stability is proportional to the ratio of the transconductance of NFET 26 relative to that of PFET 22. This value is typically larger than 2.0.
The stability of memory cell 1 is also impacted by diffusion bends in the layout of memory cell 1. FIG. 2 illustrates a prior art integrated circuit layout for memory cell 1. As illustrated in FIG. 2, an n-type diffusion region 15 is shared by NFETs 14 and 16, and an n-type diffusion region 25 is shared by NFETs 24 and 26. The bends in diffusion regions 15 and 25 are susceptible to manufacturing misalignment defects which can lead to unequal shifts in the diffusion widths of NFETs 14, 16, 24, and 26. Memory cell 1 is thus more susceptible to transistor threshold voltage Vth mismatch because the fabricated diffusion widths may be different than intended.
The figures of the drawings are not necessarily drawn to scale.